Memory with fine grain architectures

ABSTRACT

Methods, systems, and devices for memory with fine grain architectures are described. An apparatus may include a memory device, a first organic substrate, and a second organic substrate. The first organic substrate may include a plurality of first conductive lines arranged with a first pitch that may power one or more components of the memory device. The second organic substrate may be coupled with the memory device and the first organic substrate. The second organic substrate may include a plurality of second conductive lines arranged with a second pitch smaller than the first pitch and may be configured to route signals between the memory device with a host device.

CROSS REFERENCE

The present Application for Patent claims priority to U.S. ProvisionalPatent Application No. 63/107,278 by Keeth, entitled “MEMORY WITH FINEGRAIN ARCHITECTURES,” filed Oct. 29, 2020, assigned to the assigneehereof and expressly incorporated by reference herein in its entirety.

FIELD OF TECHNOLOGY

The following relates generally to one or more systems for memory andmore specifically to memory with fine grain architectures.

BACKGROUND

Memory devices are widely used to store information in variouselectronic devices such as computers, wireless communication devices,cameras, digital displays, and the like. Information is stored byprograming memory cells within a memory device to various states. Forexample, binary memory cells may be programmed to one of two supportedstates, often denoted by a logic 1 or a logic 0. In some examples, asingle memory cell may support more than two states, any one of whichmay be stored. To access the stored information, a component may read,or sense, at least one stored state in the memory device. To storeinformation, a component may write, or program, the state in the memorydevice.

Various types of memory devices and memory cells exist, includingmagnetic hard disks, random access memory (RAM), read-only memory (ROM),dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM(FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phasechange memory (PCM), self-selecting memory, chalcogenide memorytechnologies, and others. Memory cells may be volatile or non-volatile.Non-volatile memory, e.g., FeRAM, may maintain their stored logic statefor extended periods of time even in the absence of an external powersource. Volatile memory devices, e.g., DRAM, may lose their stored statewhen disconnected from an external power source.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an example of a system that supports memory with finegrain architectures in accordance with examples as disclosed herein.

FIG. 2 illustrates an example of system that supports memory with finegrain architectures in accordance with examples as disclosed herein.

FIG. 3 illustrates an example of a memory array that supports memorywith fine grain architectures in accordance with examples as disclosedherein.

FIG. 4 illustrates an example of a data channel configuration thatsupports memory with fine grain architectures in accordance withexamples as disclosed herein.

FIG. 5 illustrates an example of a memory array that supports memorywith fine grain architectures in accordance with examples as disclosedherein.

FIG. 6 illustrates an example of a memory device that supports memorywith fine grain architectures in accordance with examples as disclosedherein.

FIG. 7 illustrates an example of a timeline that supports memory withfine grain architectures in accordance with examples as disclosedherein.

FIG. 8 illustrates an example of a structure that supports memory withfine grain architectures in accordance with examples as disclosedherein.

FIG. 9 shows a block diagram of a memory device that supports memorywith fine grain architectures in accordance with examples as disclosedherein.

FIG. 10 shows a flowchart illustrating a method or methods that supportmemory with fine grain architectures in accordance with examples asdisclosed herein.

DETAILED DESCRIPTION

Some systems may include a host device coupled with a memory device byan interposer that routes signals between the host device and the memorydevice. In some examples, the type of interposer used may cause a signalto lose its strength depending on a distance a channel carrying thesignal is routed through the interposer. For example, routing the signalto a relatively far distance through the interpose may cause a signalloss as the signal is communicated between the memory device and thehost device—e.g., the signal may degrade more and more the further ittravels through the channel routed in the interposer. In such examples,the system may include additional packaging to route the signals betweenthe memory device and the host device to reduce signal loss and thedistance the channel is routed through the interposer, but this mayincrease the complexity and power consumption of the system.Additionally or alternatively, the system may include a buffer betweenthe memory device and the host device. In some examples, the buffer maycause increased power consumption in the system by the components thatreceive signals, store data, and then redrive the signals. Some memorydevices may also include relatively long conductive paths betweenvarious components and cause the system to utilize additional power toperform operations (e.g., access operations) over the long conductivepaths. For example, the memory device may consume more power when thedistance between a memory cell of the memory device and an input/output(I/O) channel is relatively large.

Systems, techniques, and devices are described herein for routingsignals between a memory device and host device utilizing a fine grainarchitecture. For example, the system may include a first organicsubstrate that provides power to one or more components of the memorydevice. The system may also include a second organic substrate that hasa finer pitch than the first organic substrate that routes signalsbetween the memory device and the host device. The second organicsubstrate may have a relatively small signal loss and decrease thecomplexity of manufacturing the system. The system may also include adefined interface (e.g., bump out or ball-out), that also reduces thecomplexity of manufacturing the system and decreases the distance ofconductive paths between various components. For example, a distancebetween a memory cell of the memory device and an I/O channel may berelatively small, thereby enabling the memory device to reduce powerconsumption. In some examples, the host device may communicate with thememory device without a buffer (e.g., point to point signaling). Byrouting signals as described herein, the memory device may increase datatransfer rates while reducing the overall power consumption of thesystem.

Features of the disclosure are initially described in the context ofsystems and dies as described with reference to FIG. 1 . Features of thedisclosure are described in the context systems, data channelconfigurations, memory arrays, memory devices, structures, and devicesas described with reference to FIGS. 2-8 . These and other features ofthe disclosure are further illustrated by and described with referenceto an apparatus diagram and a flowchart that relate to memory with finegrain architectures as described with reference to FIGS. 9 and 10 .

FIG. 1 illustrates an example of a system 100 that supports memory withfine grain architectures in accordance with examples as disclosedherein. The system 100 may include a host device 105, a memory device110, and a plurality of channels 115 coupling the host device 105 withthe memory device 110. The system 100 may include one or more memorydevices 110, but aspects of the one or more memory devices 110 may bedescribed in the context of a single memory device (e.g., memory device110).

The system 100 may include portions of an electronic device, such as acomputing device, a mobile computing device, a wireless device, agraphics processing device, a vehicle, or other systems. For example,the system 100 may illustrate aspects of a computer, a laptop computer,a tablet computer, a smartphone, a cellular phone, a wearable device, aninternet-connected device, a vehicle controller, or the like. The memorydevice 110 may be a component of the system operable to store data forone or more other components of the system 100.

At least portions of the system 100 may be examples of the host device105. The host device 105 may be an example of a processor or othercircuitry within a device that uses memory to execute processes, such aswithin a computing device, a mobile computing device, a wireless device,a graphics processing device, a computer, a laptop computer, a tabletcomputer, a smartphone, a cellular phone, a wearable device, aninternet-connected device, a vehicle controller, a system on a chip(SoC), or some other stationary or portable electronic device, amongother examples. In some examples, the host device 105 may refer to thehardware, firmware, software, or a combination thereof that implementsthe functions of an external memory controller 120. In some examples,the external memory controller 120 may be referred to as a host or ahost device 105.

A memory device 110 may be an independent device or a component that isoperable to provide physical memory addresses/space that may be used orreferenced by the system 100. In some examples, a memory device 110 maybe configurable to work with one or more different types of hostdevices. Signaling between the host device 105 and the memory device 110may be operable to support one or more of: modulation schemes tomodulate the signals, various pin configurations for communicating thesignals, various form factors for physical packaging of the host device105 and the memory device 110, clock signaling and synchronizationbetween the host device 105 and the memory device 110, timingconventions, or other factors.

The memory device 110 may be operable to store data for the componentsof the host device 105. In some examples, the memory device 110 may actas a slave-type device to the host device 105 (e.g., responding to andexecuting commands provided by the host device 105 through the externalmemory controller 120). Such commands may include one or more of a writecommand for a write operation, a read command for a read operation, arefresh command for a refresh operation, or other commands.

The host device 105 may include one or more of an external memorycontroller 120, a processor 125, a basic input/output system (BIOS)component 130, or other components such as one or more peripheralcomponents or one or more input/output controllers. The components ofhost device 105 may be coupled with one another using a bus 135.

The processor 125 may be operable to provide control or otherfunctionality for at least portions of the system 100 or at leastportions of the host device 105. The processor 125 may be ageneral-purpose processor, a digital signal processor (DSP), anapplication-specific integrated circuit (ASIC), a field-programmablegate array (FPGA) or other programmable logic device, discrete gate ortransistor logic, discrete hardware components, or a combination ofthese components. In such examples, the processor 125 may be an exampleof a central processing unit (CPU), a graphics processing unit (GPU), ageneral purpose GPU (GPGPU), or an SoC, among other examples. In someexamples, the external memory controller 120 may be implemented by or bea part of the processor 125.

The BIOS component 130 may be a software component that includes a BIOSoperated as firmware, which may initialize and run various hardwarecomponents of the system 100 or the host device 105. The BIOS component130 may also manage data flow between the processor 125 and the variouscomponents of the system 100 or the host device 105. The BIOS component130 may include a program or software stored in one or more of read-onlymemory (ROM), flash memory, or other non-volatile memory.

The memory device 110 may include a device memory controller 155 and oneor more memory dies 160 (e.g., memory chips) to support a desiredcapacity or a specified capacity for data storage. Each memory die 160may include a local memory controller 165 (e.g., local memory controller165-a, local memory controller 165-b, local memory controller 165-A) anda memory array 170 (e.g., memory array 170-a, memory array 170-b, memoryarray 170-N). A memory array 170 may be a collection (e.g., one or moregrids, one or more banks, one or more tiles, one or more sections) ofmemory cells, with each memory cell being operable to store at least onebit of data. A memory device 110 including two or more memory dies maybe referred to as a multi-die memory or a multi-die package or amulti-chip memory or a multi-chip package.

The memory die 160 may be an example of a two-dimensional (2D) array ofmemory cells or may be an example of a three-dimensional (3D) array ofmemory cells. A 2D memory die 160 may include a single memory array 170.A 3D memory die 160 may include two or more memory arrays 170, which maybe stacked on top of one another or positioned next to one another(e.g., relative to a substrate). In some examples, memory arrays 170 ina 3D memory die 160 may be referred to as decks, levels, layers, ordies. A 3D memory dies 160 may include any quantity of stacked memoryarrays 170 (e.g., two high, three high, four high, five high, six high,seven high, eight high). In some 3D memory dies 160, different decks mayshare at least one common access line such that some decks may share oneor more of a word line, a digit line, or a plate line.

The device memory controller 155 may include circuits, logic, orcomponents operable to control operation of the memory device 110. Thedevice memory controller 155 may include the hardware, the firmware, orthe instructions that enable the memory device 110 to perform variousoperations and may be operable to receive, transmit, or executecommands, data, or control information related to the components of thememory device 110. The device memory controller 155 may be operable tocommunicate with one or more of the external memory controller 120, theone or more memory dies 160, or the processor 125. In some examples, thedevice memory controller 155 may control operation of the memory device110 described herein in conjunction with the local memory controller 165of the memory die 160.

In some examples, the memory device 110 may receive data or commands orboth from the host device 105. For example, the memory device 110 mayreceive a write command indicating that the memory device 110 is tostore data for the host device 105 or a read command indicating that thememory device 110 is to provide data stored in a memory die 160 to thehost device 105.

A local memory controller 165 (e.g., local to a memory die 160) mayinclude circuits, logic, or components operable to control operation ofthe memory die 160. In some examples, a local memory controller 165 maybe operable to communicate (e.g., receive or transmit data or commandsor both) with the device memory controller 155. In some examples, amemory device 110 may not include a device memory controller 155, and alocal memory controller 165, or the external memory controller 120 mayperform various functions described herein. As such, a local memorycontroller 165 may be operable to communicate with the device memorycontroller 155, with other local memory controllers 165, or directlywith the external memory controller 120, or the processor 125, or acombination thereof. Examples of components that may be included in thedevice memory controller 155 or the local memory controllers 165 or bothmay include receivers for receiving signals (e.g., from the externalmemory controller 120), transmitters for transmitting signals (e.g., tothe external memory controller 120), decoders for decoding ordemodulating received signals, encoders for encoding or modulatingsignals to be transmitted, or various other circuits or controllersoperable for supporting described operations of the device memorycontroller 155 or local memory controller 165 or both.

The external memory controller 120 may be operable to enablecommunication of one or more of information, data, or commands betweencomponents of the system 100 or the host device 105 (e.g., the processor125) and the memory device 110. The external memory controller 120 mayconvert or translate communications exchanged between the components ofthe host device 105 and the memory device 110. In some examples, theexternal memory controller 120 or other component of the system 100 orthe host device 105, or its functions described herein, may beimplemented by the processor 125. For example, the external memorycontroller 120 may be hardware, firmware, or software, or somecombination thereof implemented by the processor 125 or other componentof the system 100 or the host device 105. Although the external memorycontroller 120 is depicted as being external to the memory device 110,in some examples, the external memory controller 120, or its functionsdescribed herein, may be implemented by one or more components of amemory device 110 (e.g., a device memory controller 155, a local memorycontroller 165) or vice versa.

The components of the host device 105 may exchange information with thememory device 110 using one or more channels 115. The channels 115 maybe operable to support communications between the external memorycontroller 120 and the memory device 110. Each channel 115 may beexamples of transmission mediums that carry information between the hostdevice 105 and the memory device. Each channel 115 may include one ormore signal paths or transmission mediums (e.g., conductors) betweenterminals associated with the components of system 100. A signal pathmay be an example of a conductive path operable to carry a signal. Forexample, a channel 115 may include a first terminal including one ormore pins or pads at the host device 105 and one or more pins or pads atthe memory device 110. A pin may be an example of a conductive input oroutput point of a device of the system 100, and a pin may be operable toact as part of a channel.

Channels 115 (and associated signal paths and terminals) may bededicated to communicating one or more types of information. Forexample, the channels 115 may include one or more command and address(CA) channels 186, one or more clock signal (CK) channels 188, one ormore data (DQ) channels 190, one or more other channels 192, or acombination thereof. In some examples, signaling may be communicatedover the channels 115 using single data rate (SDR) signaling or doubledata rate (DDR) signaling. In SDR signaling, one modulation symbol(e.g., signal level) of a signal may be registered for each clock cycle(e.g., on a rising or falling edge of a clock signal). In DDR signaling,two modulation symbols (e.g., signal levels) of a signal may beregistered for each clock cycle (e.g., on both a rising edge and afalling edge of a clock signal). In some examples, the DQ channels 190may be coupled with the memory device via data pins (e.g., DQ pins).

In some examples, CA channels 186 may be operable to communicatecommands between the host device 105 and the memory device 110 includingcontrol information associated with the commands (e.g., addressinformation). For example, commands carried by the CA channel 186 mayinclude a read command with an address of the desired data. In someexamples, a CA channel 186 may include any quantity of signal paths todecode one or more of address or command data (e.g., eight or ninesignal paths).

In some examples, clock signal channels 188 may be operable tocommunicate one or more clock signals between the host device 105 andthe memory device 110. Each clock signal may be operable to oscillatebetween a high state and a low state, and may support coordination(e.g., in time) between actions of the host device 105 and the memorydevice 110. In some examples, the clock signal may be single ended. Insome examples, the clock signal may provide a timing reference forcommand and addressing operations for the memory device 110, or othersystem-wide operations for the memory device 110. A clock signaltherefore may be referred to as a control clock signal, a command clocksignal, or a system clock signal. A system clock signal may be generatedby a system clock, which may include one or more hardware components(e.g., oscillators, crystals, logic gates, transistors).

In some examples, data channels 190 may be operable to communicate oneor more of data or control information between the host device 105 andthe memory device 110. For example, the data channels 190 maycommunicate information (e.g., bi-directional) to be written to thememory device 110 or information read from the memory device 110.

The channels 115 may include any quantity of signal paths (including asingle signal path). In some examples, a channel 115 may includemultiple individual signal paths. For example, a channel may be x4(e.g., including four signal paths), x8 (e.g., including eight signalpaths), x16 (including sixteen signal paths), etc.

In some examples, the one or more other channels 192 may include one ormore error detection code (EDC) channels. The EDC channels may beoperable to communicate error detection signals, such as checksums, toimprove system reliability. An EDC channel may include any quantity ofsignal paths.

In some examples, the memory device 110 may be coupled with the hostdevice 105 through a first organic substrate. That is, the first organicsubstrate may include the channels 115. The first organic substrate maybe deposited on a second organic substrate that is configured to routepower to the memory device 110. The first organic substrate may have afiner pitch (e.g., a pitch less than) than the second organic substrate.The first organic substrate may have a relatively small signal loss andmay thus be used to configure the host device 105 and memory device 110to have a point-to-point connection. That is, the memory device 110 maynot include buffers to buffer signals received or transmitted to thehost device. Additionally, the memory device 110 may be coupled with thefirst organic substrate through a plurality of interfaces, eachinterface having a defined preconfigured bump-out or ball-out. Thispoint-to-point connection and the plurality of connections via theinterfaces may reduce power consumption and increase a rate of datatransfer between the memory device 110 and the host device 105. Forexample, the increased interfaces may reduce the distance data is drivenfrom the memory cell to an input/output (I/O) area.

FIG. 2 illustrates an example of a system 200 that supports memory withfine grain architectures in accordance with examples as disclosedherein. The system 200 may be an example of system 100 as described withreference to FIG. 1 . System 200 may include a host device 205 and amemory device 210 which may be examples of host device 105 and memorydevice 110, respectively, as described with reference to FIG. 1 . Hostdevice 205 may be coupled with the memory device 210 using a substrate220. The substrate 220 may be coupled with a substrate 215. The memorydevice 210 may include an operation layer 225 and memory layers 230-athrough 230-h. Eight (8) memory layers 230 are shown in FIG. 2 forillustrative purposes only. The memory device 210 may include anyquantity of memory layers 230 including one, two, three, four, five,six, seven, eight, nine, ten, eleven, twelve, thirteen, fourteen,fifteen, sixteen, seventeen or more layers.

Host device 205 may be configured to communicate signals, commands,requests, or data to the memory device 210 via the substrate 220 andconductive lines 250 (e.g., channels 115 as described with reference toFIG. 1 ). In some examples, the host device 205 may be configured tocommunicate directly with a memory cell or memory array of the memorydevice 210. That is, the system 200 may include point-to-pointconnections between the host device 205 and the memory layers 230 of thememory device 210 without the signals been buffered by a buffer layer ofthe memory device 210. In such examples, the host device 205 may beconfigured to communicate signals along conductive lines 250 directly toa DQ pin of the memory device 210 based on a memory address associatedwith the signal. For example, the host device 205 may communicate asignal to a first DQ pin based on a first memory address associated withan access command (e.g., a read, write, or refresh command). In suchexamples, by sending a signal directly to the DQ pins, the host device205 may effectively be communicating directly with the memory cells. Byenabling the host device 205 to have a point-to-point connection withthe memory device 210, the overall power consumption of the system 200may decrease and the performance time of the system 200 may increase.That is, the lack of a buffer layer may rid the system 200 of extraneousdrivers and receivers configured to buffer signals between the hostdevice 205 and the memory device 210 reducing power consumption andincreasing a rate of data transfer.

Substrate 215 may include conductive line(s) 240 that are configured tosupply power to one or more components of the memory device 210. Theconductive line(s) 240 may be configured to supply a ground voltage or avoltage with a magnitude larger than a ground voltage. In some examples,the substrate 215 may include pins (e.g., channels or throughsilicon-vias (TSVs)) 245 to supply the power from the conductive line(s)240 to the memory device 210. That is, although not shown for clarity,the pins 245 extend through the memory device 210 up to the upper mostmemory layer, the memory layer 230-h. The pins 245 may be configured tosupply the power to the memory device 210 straight through the operationlayer 225 and the memory layers 230 (e.g., a straight-up orperpendicular configuration). That is, the pins 245 may be perpendicularto the memory device 210 and be at a same column position for eachmemory layer 230 and thus may provide power to each memory layer 230 atthe same column position.

In some examples, the substrate 215 may be an organic substrate. In suchexamples, the substrate 215 may be manufactured with a pitch constraintthat is greater than a pitch constraint of the substrate 220. Forexample, the substrate 215 may have a pitch greater than or equal to ten(10) micrometers (μm). Additionally, the substrate 215 may bemanufactured with a line parameter or space parameter (e.g., a width andpitch of a metal trace) greater than a line parameter and spaceparameter of the substrate 220. For example, the substrate 215 may havea line parameter or a space parameter greater than or equal to ten (10)μm.

Substrate 220 may be coupled with the memory device 210, the host device205, and the substrate 215. In some examples, the substrate 220 mayinclude conductive lines 250 to route signals between the memory device210 and the host device 205 (e.g., routing commands, requests, or data).In some examples, the substrate 220 may be a fine pitch organicsubstrate. Substrate 220 may be manufactured as a polyimide spin-onorganic polymetric dielectric. That is, substrate 220 may be a polyimidedielectric that is deposited on to the substrate 215 utilizing a spin-onapproach. In other examples, the substrate 220 may be deposited on thesubstrate 215 utilizing other deposition techniques (e.g., chemicalvapor deposition (CVD), physical vapor deposition (PVD), or anycombination thereof). In either example, the substrate 220 may bedeposited directly on to substrate 215—e.g., without ball packaging orother column supports between the substrate 215 and the substrate 220.In some examples, the conductive lines 250 may have an impedance lessthan an impedance of a conductive line of a silicon interposer. That is,the conductive lines 250 may experience lower signal loss thanconductive lines of a silicon interposer. This may reduce the complexityof manufacturing conductive lines 250 to route signals between the hostdevice 205 and the memory device 210—e.g., this may reduce the usage offan out packaging (FOP) in the operation layer 225 that other solutionsmay use. In some examples, the substrate 220 may be manufactured with aline parameter, space parameter, and a pitch less than the respectiveline parameter, space parameter, and pitch of the substrate 215. Forexample, the line parameter, space parameter, and pitch of the substrate220 may be less than or equal to two (2) μm.

Memory device 210 may be configured to store data or information forhost device 205—e.g., the host device 205 may write data to or read datafrom the memory device 210. In some examples, the memory device 210 mayinclude an operation layer 225. For example, the operation layer 225 maybe an example of a built-in self-test (BIST) layer. The operation layer225 may be configured to provide one or more circuits to operate thememory device 210. For example, the operation layer 225 may include oneor more self-test circuits to test aspects of the memory device 210. Insome examples, the operation layer 225 may not have buffers. That is,because the system 200 utilizes a point-to-point connection, theoperation layer 225 may not have drivers and receivers configured toreceive signals from the host device 205, a buffer, and additionaldrivers configured to receive signals from the memory device 210. Byutilizing a point-to-point connection and not buffering signals, thesystem 200 may reduce power consumption.

The memory device 210 may also include one or more memory layers 230. Insome instances, the memory layers 230 may be manufactured on top of(e.g., stacked on top of) the operation layer 225. In some examples, thememory layers 230 may be examples of memory arrays (e.g., memory arrays170 as described with reference to FIG. 1 ). In other examples, thememory layers 230 may be examples of memory dice (e.g., memory die 160as described with reference to FIG. 165 ). In either example, the memorylayers 230 may include a plurality of memory cells configured to storedata. The memory layers 230 may be coupled with each other by TSVs 235and bond pads. In some examples, the TSVs 235 may communicate data fromthe host device 205 and the interface 255 to a memory layer 230 byutilizing a non-perpendicular signal flow configuration (e.g., awaterfall configuration). For example, each memory layer 230 may includeone or more column positions that are common to each memory layer 230.In some cases, the memory layer 230-b may be configured to route datafrom a TSV 235-a in a first column position to a TSV 235-b at a secondcolumn position down to the interface 255. The configuration of datatransfer between the TSVs 235 in the waterfall configuration isdescribed in additional detail with reference to FIG. 6 .

In some examples, the memory device 210 is coupled with the substrate220 by the interface 255. In some examples, the interface 255 may have aspecific bump out or ball-out—e.g., the interface 255 may have a patternof contacts configured to route the signals from the conductive lines250. In some cases, the interface 255 may be configured to route thesignals based on channels or routing patterns of I/O areas located inthe memory device 210. The memory device 210 may include a plurality ofI/O areas such that a distance between a memory cell in the memorydevice 210 and an I/O areas of the plurality of I/O areas is relativelysmall. By having the relatively small distance between the memory celland the I/O areas, the memory device 210 may reduce power consumptionassociated with driving data between the I/O areas and the memory cell.Additional details related to the I/O areas and the ball-out or bump-out(e.g., the pattern) are described with reference to FIGS. 3-5 .

FIG. 3 illustrates an example of a memory array 300 that supports memorywith fine grain architectures in accordance with examples as disclosedherein. The memory array 300 may be an example of a memory die 160described with reference to FIG. 1 . In some cases, the memory array 300may be referred to as a memory die, an array of memory cells, a deck ofmemory cells, or a memory layer 230 described with reference to FIG. 2 .The various components of the memory array 300 may be configured tofacilitate high bandwidth data transfer between a host device (e.g.,host device 105 as described with reference to FIG. 1 ) and a memorydevice (e.g., memory device 210 as described with reference to FIG. 2 )with which the memory array 300 is associated.

The memory array 300 may include a plurality of banks 305 of memorycells (as represented by the white boxes), a plurality of input/output(I/O) areas 310 (sometimes referred to as I/O stripes or I/O regions)traversing the memory cells of the memory array 300, and a plurality ofdata channels 315 that couple the memory array 300 with the host device.In some examples, the plurality of data channels 315 may route through afirst organic substrate (e.g., substrate 220 as described with referenceto FIG. 2 ). The data channels 315 may provide a point-to-pointconnection between the memory array 300 and the host device—e.g., theremay be no buffering of signals communicated between the memory array 300and the host device. Additionally or alternatively, the host device maydirectly send the signals to memory array 300 in using thepoint-to-point connection to read data from or write data to a memorycell of the memory array 300. In some examples, there may be a first I/Oarea 311 that extends in a first direction and there may be one or moreI/O areas 310 that extend in a second direction of different than thefirst direction. In some cases, the first direction is orthogonal to thesecond direction. The I/O areas 311 and 310 may be devoid of memorycells and may be occupied with TSVs and/or other conductive paths usedto route signals. For example, the I/O areas 310 and 311 may includeconductive paths for power, for ground, for DQ channels, for CAchannels, and other channels as described in FIG. 4 and other figures.Additional details about layouts of conductive paths in the I/O areas310 and 311 are described in more detail with reference to FIG. 5 .

Each of the banks 305 of memory cells may include a plurality of memorycells configured to store data. The memory cells may be DRAM memorycells, FeRAM memory cells, or other types of memory cells. At leastsome, if not each, of the plurality of I/O areas 310 may include aplurality of power pins and ground pins configured to couple the memorycells of the memory array 300 with power and ground. In some examples,the plurality of ground pins and power pins may be examples of theground pins and power pins as described with reference to FIG. 2 (e.g.,the pins 245). The ground and power pins may be supplied by a voltageprovided by a second organic substrate (e.g., substrate 215 as describedwith reference to FIG. 2 ).

The memory array 300 may be divided into cell regions 320 associatedwith different data channels 315. For example, a single data channel 315may be configured to couple a single cell region 320 with the hostdevice. The pins of the I/O channel may be configured to couple multiplecell regions 320 of the memory array 300 to power, ground, virtualground, and/or other supporting components.

To provide a high throughput of data (e.g., multiple TB/s) between ahost device (not shown) and the memory array 300, a path length betweenany given memory cell and the host interface may be shortened, ascompared to previous solutions. In addition, shortening the data pathbetween any given memory cell and the host device may also reduce thepower consumed during an access operation (e.g., read operation or writeoperation) of that given memory cell. Different architectures and/orstrategies may be employed to reduce the size of the data path. Forexample, the memory array 300 may be coupled with the first substratethrough a plurality of interfaces, each interface including multiple I/Ochannels and areas. This may reduce the distance between a given memorycell and the I/O channels. In such cases, the memory array 300 mayreduce power consumption with the shorter distance between the memorycell and the I/O channels as compared with other solutions. The memoryarray 300 may also perform faster accesses (e.g., read, write, orrefresh accesses) on the memory cells given the distance is reduced.

In some examples, the memory array 300 may be partitioned into aplurality of cell regions 320. Each cell region 320 may be associatedwith a data channel 315. Two different types of cell region 320 areillustrated, as one example, but the entire memory array 300 may bepopulated with any quantity of cell regions 320 having any shape. A cellregion 320 may include a plurality of banks 305 of memory cells. Theremay be any quantity of banks 305 in a cell region 320. For example, thememory array 300 illustrates a first cell region 320 that may includeeight banks 305 and a second cell region 320-a that may include sixteenbanks 305-a.

Other quantities of banks in the cell region are possible, however(e.g., two, three, four, five, six, seven, eight, nine, ten, eleven,twelve, thirteen, fourteen, fifteen, sixteen, seventeen, eighteen,nineteen, twenty, twenty-one, twenty-two, twenty-three, twenty-four,twenty-five, twenty-six, twenty-seven, twenty-eight, twenty-nine,thirty, thirty-one, thirty-two, etc.). The size of the cell region 320may be selected based on the bandwidth constraints of the host device,the power usage of the host device or the memory device, the size of thedata channel, the parameters of the substrate used to couple the memoryarray 300 with the host device, a data rate associated with the datachannel, other considerations, or any combination thereof. In somecases, the memory array 300 may be partitioned such that each cellregion 320 may be the same size. In other cases, the memory array 300may be partitioned such that the memory array 300 may have cell regions320 of different sizes.

A data channel 315 (associated with a cell region) may include aquantity of pins for coupling the memory cells of the cell region 320with the host device. At least a portion of the data channel 315 maycomprise channels of the substrate (e.g., the first organic substrate).The data channel 315 may include a data width specifying how many datapins 325 (sometimes referenced as DQ pins) are in the data channel 315.For example, a data channel may have a channel width of two data pins(e.g., X2 channel), four data pins (e.g., X4 channel), eight data pins(e.g., X8 channel), sixteen data pins (e.g., X16 channel), etc. The datachannel may also include at least one CA pin 330 (sometimes referred toas a C/A pin). Each memory cell in the cell region 320 may be configuredto transfer data to and from the host device using the data pins 325 andCA pins 330 associated with the cell region 320. The data channel 315may also include a clock pin (e.g., CLK or WCLK) and/or a read clock pinor a return clock pin (RCLK).

In some cases, the channel width of the data channel 315 may vary basedon the parameters of the substrate (e.g., the organic substrate) used tocouple the memory device and the host device. For example, if a firstsubstrate (the fine pitch organic substrate) having a first line andspace parameter is used to couple the memory device and the host device,then the channel width may be a first width. In another example,however, if a different substrate (e.g., an organic substrate with adifferent line and space parameter or pitch) is used to couple thememory device and the host device, then the channel width may be secondwidth. An I/O interface (not shown in FIG. 3 ) of the memory array 300may be configured to support both channel widths. That is, the I/Ointerface may have a pattern of routes to communicate data to and fromthe memory device. In some examples, the first substrate is coupled withthe memory device through interfaces that mirror the pattern of the I/Ointerface. In some instances, to maintain data bandwidth, datathroughput, or data accessibility, different modulation schemes may beused to communicate data across channels with different widths. Forexample, PAM4 may be used to modulate signals communicated across an X4channel and NRZ may be used to modulate signals communicated across anX8 channel.

The I/O area 310 (e.g., the I/O stripe) may, in some cases, bisect thebanks 305 of memory cells in the cell region 320. In this manner, thedata path for any individual memory cell may be shortened. That is, witha plurality of I/O areas 310, the distance data is driven between thememory cell and the I/O area may be reduced. The I/O areas 310 may bedispersed across the memory array 300 strategically to reduce thedistances.

FIG. 4 illustrates an example of a data channel configuration 400 thatsupports memory with fine grain architectures in accordance withexamples as disclosed herein. For example, a first data channelconfiguration 405 illustrates an independent data channel 410 thatservices a first cell region 415. A second data channel configuration420 illustrates a data channel pair 425 where data channels for two cellregions (e.g., second cell region 430 and third cell region 435) shareclock pins, error detection code (EDC) pins, and spare pins. In somecases, the channel width of the data channel configurations may beadjustable based at least in part on a parameter associated with a firstsubstrate (e.g., a substrate 220 as described with reference to FIG. 2 )used to couple a host device (e.g., host device 105 as described withreference to FIG. 1 ) with a memory device (e.g., memory device 210 asdescribed with reference to FIG. 2 ). For example, if an organicsubstrate has a first line and space parameter, the data channel mayhave a first channel width, and, if the organic substrate has a secondline and space parameter, the data channel may have a second channelwidth that is larger than the first channel width (e.g., twice as big).

The data channel 410 illustrates a data channel for a stacked memorydevice that includes eight layers that has a channel width of four(e.g., there are four data pins). In other examples, the channel widthmay be more than four or less than four (e.g., eight data pins). Eachrow of pins in the data channel 410 may be associated with a cell regionin a separate layer. The first cell region 415 illustrates a cell regionof a single layer. As such, the first cell region 415 may be associatedwith a single row of the pins of the data channel 410. The quantity ofpins in a data channel may be based on the quantity of layers in thememory device because a single data channel may be configured to couplewith a given layer.

In some cases, the term data channel may refer to pins associated with asingle cell region of a single layer. The term data channel may refer topins associated with multiple cell regions across multiple layers. Insome examples, data channels may be coupled with a single cell region(e.g., without being coupled with another cell region) of any givenlayer or memory die. The same may also be true for the data channel pair425 of the second data channel configuration 420. The data channel pair425 shows pins for cell regions across multiple layers of the memorydevice. Although data channel 410 and data channel pair 425 shown may beassociated with cell regions in eight layers, any quantity of layers arepossible. For example, the data channel 410 and data channel pair 425may be associated with cell regions in one, two, three, four, five, six,seven, eight, nine, ten, eleven, twelve, thirteen, fourteen, fifteen, orsixteen (or more) layers of the memory device.

The data channel 410 includes four data pins (DQ0-DQ4), a clock pin (CLKor a WCLK signal), a read clock pin or return clock pin (RCLK), and acommand/address pin (CA). The data channel 410 may also include an EDCpin and a spare pin that is utilized when another pin is defective. Inother cases, the data channel may have a different rank or differentchannel width. In such situations, the quantity of data pins may bedifferent. For example, the data channel 410 may have a channel width ofeight and may include eight data pins. Any quantity of data pinsassociated with a region are contemplated by this disclosure. The datachannel 410 may include any quantity of C/A pins. For example, the datachannel 410 may include one, two, three, or four C/A pins. In somecases, the data channel 410 may include an error correction code (ECC)pin (not shown) for facilitating error detection and correctionprocedures. The data channel 410 may also include a data bus inversion(DBI) pin (not shown) for limiting the quantity of simultaneoustransitioning signals and bias the state of the transmitted data towardsa preferred level.

The data channel pair 425 may be similarly embodied as the data channel410 except that two data channels associated with two different cellregions may be configured to share clock pins, EDC pins, and spare pins.As such, in the data channel pair 425, the clock pins (e.g., CLK, RCLK,or WCK), EDC pins, and spare pins may be coupled with two cell regionsof the same layer of the memory device, while the other pins of the datachannel pair 425 (e.g., DQ pins, C/A pins, ECC pins) may be coupled witha single cell region of a single layer. For example, the illustrateddata channel pair 425 may have a width of four. As such, four data pinsand one C/A pin (e.g., CH0-Layer0) may be coupled with the second cellregion 430 and four data pins and one C/A pin (CH8-Layer0) may becoupled with the third cell region 435.

The data channel pair 425 may reduce the complexity of a memory deviceand the power consumption of the memory device. For example, by sendinga single set of clock signals to two cell regions in a layer, it mayreduce the quantity of clock components in the memory device and therebyreduce the amount of power to drive the clock signals. In some examples,the second cell region 430 and the third cell region 435 may share thespare pin. In such examples, the second cell region 430 and the thirdcell region 435 may share a logic (e.g., a multiplexer (MUX)) that isconfigured to communicate with either the second cell region 430 or thethird cell region 435 depending on which cell region is utilizing thespare pin at a given time—e.g., the MUX may communicate with the secondcell region 430 when the second cell region is utilizing the spare pin.

In some cases, the channel widths of the data channels may beconfigurable based on parameters of the substrate used to couple thehost device and the memory device and/or the type of modulation schemeused to modulate signals communicated between the host device and thememory device. Different substrates (e.g., the fine pitch organicsubstrate) with different parameters may be able to support differentsignal frequencies.

The memory device may be configured to couple with interfaces dependingon the pattern utilized by the interface to route signals. For example,the terminuses of the channels 410 or 425 may be in a first patternindicating the routing of the signals to different locations in thememory device. In such cases, the memory device may couple with aninterface that has a second pattern of routing signals that is the sameas the first pattern. That is, the memory device may be coupled with afine pitch organic substrate that is manufactured with a bump-out or aball-out pattern that is the same as the routing pattern in the channels410 or 415 (e.g., the pattern of the I/O areas). Such a configurationmay improve the compatibility between the memory device and thesubstrate (e.g., the fine pitch organic substrate). For example, thememory device coupling with interfaces with the same pattern may enablethe memory device to have an increased quantity of channels 410 or 425dispersed throughout the memory device. In such examples, the distancebetween the memory cells and the channels 410 or 425 may be reduced.That is, the average distance data has to be driven between a memorycell and a channel 410 or 425 may be reduced compared with previoussolutions. The memory device may consume less power and increase a rateof data transfer to and from the host device through the fine pitchorganic substrate—e.g., the shorter average distances enable decrease ina ratio of picojoules utilized while transferring a bit of data.

TABLE 1 Solo Channel Channel Pair 8 DQ pins 16 DQ pins (8 per region) 1DBI pin 2 DBI pins (1 per region) 1 ECC pin 2 ECC pins (1 per region) 1CA pin 2 CA pins (1 per region) 1 WCK pin 1 WCK pin (shared by regions)1 RCK pin 1 RCK pin (shared by regions) 1 EDC pin 1 EDC pin (shared byregions) 1 spare pin 1 spare pin (shared by regions)

Table 1 provides two examples of channel layouts, a first exampleshowing a channel that supports one region of memory cells and a secondexample showing a second channel that supports two regions of memorycells. The second example may be an example of a channel pair where somepins or signals are shared by both regions of memory cells and some pinsor signals are dedicated to a certain memory region. If a memory deviceincludes 8 regions of memory cells per memory layer and has a stack thatis eight memory layers high, there may be a total of 64 regions ofmemory cells in the memory device. In the first example of a solochannel such a configuration may result in 1920 total pins or conductivepaths in the memory device. In the second example of a shared channelsuch a configuration may result in total pins or conductive in thememory device. Thus, the channel pair example may result in fewerconductive paths between the host device and the memory device. In somecases, it may be advantageous to be below certain pin counts to increasecompatibly with some host devices or interfaces. Examples of conductivepin quantity thresholds may include 1,704 conductive paths or 1,624conductive paths.

FIG. 5 illustrates an example of a memory array 500 that supports memorywith fine grain architectures in accordance with examples as disclosedherein. The memory array 500 may be an example of the memory array 170as described with reference to FIG. 2 or the memory array 300 describedwith reference to FIG. 3 . The memory array 500 may illustrate anexample of a physical layout of the conductive paths within an I/O areawhile the memory array 300 may illustrate a more simplified version ofthe conductive paths with an I/O area. The memory array 500 may be anexample of a memory layer 230 of a memory device as described withreference to FIG. 2 . The memory array 500 may include an I/O area(e.g., channels, stripes, or interfaces) 520 and I/O areas 515. The I/Oareas 515 and 520 may occupy areas of memory array 500 that are devoidof memory cells. In some examples, memory array 500 may also be referredto as memory die.

In some cases, the memory array 500 may be coupled with a fine pitchorganic substrate (e.g., substrate 220 as described with reference toFIG. 2 ). That is, the memory array 500 may receive signals directlyfrom a host device (e.g., host device 105 as described with reference toFIG. 1 ) through the fine pitch organic substrate via conductive lines(e.g., conductive lines 250 as described with reference to FIG. 2 ). Thememory array 500 may be coupled with the fine pitch organic substrate bya first interface (e.g., interface 255 as described with reference toFIG. 2 ). The first interface may have bump-out or ball-out pattern thatcontacts the memory array 500. The first interface pattern may beconfigured to route signals to different regions of the memory array500. In some examples, the pattern contacts may be positioned below anI/O area 515. That is, the pattern of contacts may be based on thelayout (e.g., floorplan) of the I/O area 515 to route signals from thehost device to the memory cells in the memory array 500. By having theI/O area 515 routing patterns match the bump-out or ball-out of theinterfaces, the compatibility between the memory array and the finepitch organic substrate may be increased.

In some examples, a memory array 500 may include a plurality of regionsof memory cells. In some cases, each region of the plurality of regionsof memory cells may include one or more banks of memory cells (e.g.,portions of memory cells). The memory array 500 may include multiple I/Oareas 515 and 520 that are distributed (e.g., dispersed) throughout thememory array 500 such that the memory cells are located relativity nearthe I/O areas 515 and 520. For example, the memory array 500 may includean I/O area 520 that extends through the memory array 500 vertically.The vertical I/O area 520 may divide the memory array 500 into a firstportion and a second portion of memory cells.

In some examples, the memory array 500 may include multiple I/O areas515 that extend in a horizontal direction through the memory array 500.The horizontal I/O area 515 may extend through both the first portionand the second portion of memory cells. The portion of the horizontalI/O area 515 that extends through the first portion (e.g., I/O area515-a) may include a plurality of channels. For example, the I/O area515-a may include a first plurality of channels (e.g., TSVs 235 or pins245 as described with reference to FIG. 2 ) configured to communicatewith an area of memory cells 505 and a second plurality of channels tocommunicate with an area of memory cells 510. In some examples, the areaof memory cells 505 and 510 may be each be examples of a bank of memorycells. In some example, the first plurality of channels and the secondplurality of channels may share common channels (e.g., as described withreference to FIG. 4 ). That is, rather than having a single plurality ofchannels dedicated exclusively for area of memory cells 505 and 510, thefirst plurality and second plurality of channels may share channels.This may reduce the overall quantity of signals communicated andchannels utilized throughout the memory die—e.g., by sharing channels,the total signals utilized may decrease. For example, channelscommunicating clock signals (e.g., WCK, RCK, or CLK (not shown)) anderror detection code (e.g., EDC) signals may be shared. Additionally,the first plurality of channels and the second plurality of channels mayalso share a spare channel. In some examples, the spare channel mayshare a common logic (e.g., a multiplexer (MUX)) such that the logic isconfigured to communicate with either the first plurality of channels orthe second plurality of channels depending on which plurality isutilizing the spare channel at a given time. The remaining channels(e.g., channels DQ0-DQ7, ECC, CA, and data bus inversion (e.g., DBI))may be dedicated exclusively to an area of memory cells—e.g., a set ofthe channels described (DQ0-DQ7, ECC, CA, and DBI) may be exclusive tothe area of memory cells 505.

The plurality of channels may be configured to communicate various typesof signals to and from the memory array 500. For example, some channelsthe plurality of channels may be configured to communicate a groundsignal 525 (e.g., a ground voltage) and some channels of the pluralityof channels may be configured to communicate a power signal 530 (e.g., avoltage). The signals 525 and 530 may originate from an organicsubstrate (e.g., substrate 215 as described with reference to FIG. 2 ).In some examples, the ground signal 525 may be referred to as a groundchannel, a ground signal path, or a ground conductive path and the powersignal 530 may be referred to as a power channel, a power signal, or apower conductive path. In some examples, some channels of the pluralityof channels may be configured to communicate communication signals 535between the host device and memory device. The signals 535 may be routedthrough a second organic substrate with a fine pitch (e.g., substrate220 as described with reference to FIG. 2 ). In some examples, thecommunication signals 535 may be referred to as communication channels,communication signal paths, or communication conductive paths. Examplesof the communication signals 535 may include DQ signals, CA signals, DBIsignals, ECC signals, EDC signals, WCK signals, and RCK signals, amongother signals.

In some examples, each row of the plurality of channels (e.g., the rowof channels for the DQ0 pin) may communicate signals for differentlayers (e.g., memory layers 230 as described with reference to FIG. 2 )in the memory device. For example, the channel communicating signal 540may be a channel communicating with a first layer (e.g., memory layer230-a) while the channel communicating signal 545 may be a channelcommunicating with an eighth layer (e.g., memory layer 230-h). In suchexamples, the channels communicating the signals between signal 540 and545 may communicate with a layer between the first layer and the eighthlayer (e.g., memory layers 230-b through memory layers 230-g). In someexamples, because of the non-perpendicular data flow structure, thetop-most channel remains dedicated to that particular level (e.g., thechannel communicating signal 545 may remain dedicated to the eighthlayer, even if the channel extends through the remaining layers).Further details of the non-perpendicular data flow structure (e.g.,waterfall structure) and arrangement of channels throughout the layersis described with reference to FIG. 6 .

The memory array 500 may be coupled with the fine pitch organicsubstrate through multiple interfaces—e.g., there may be multiplevertical I/O areas 520 distributed throughout the memory array 500.Additionally, there may be multiple I/O areas 515 dispersed throughoutthe memory array 500. This may enable the memory array 500 to havemultiple connection points with the host device, decreasing the distancedata has to be driven to or from a memory cell based on a receivedsignal. That is, in some memory devices there may be a centralizedinterface that communicates some or all of the data from the memorycell. In such examples, data routed from distant memory cells (e.g.,memory cells far from the interface) may be driven relatively farincreasing the power consumption and reducing the rate of transfer(e.g., it may take additional power and time to drive the data from thedistant memory cell to the centralized interface). As described herein,with multiple interfaces and I/O areas distributed throughout the memoryarray 500, the distance data is driven/routed from a given memory cellto the interface may be relatively small. That is, with a dedicatedfirst plurality of channels for the area of memory cells 505, data maybe quickly driven from the memory cell to the I/O area 515 as thedistance is relatively small. For example, the memory cell may becoupled with a first conductive line coupling the memory cell with theI/O area 515. Then the I/O area 515 may communicate signals to theinterface between the memory array 500 and the host device. Theconductive lines in the fine pitch organic substrate may then transferthe data between the interface and the host device. The decreaseddistances may decrease power consumption and increase a rate of datatransfer for the memory array 500.

FIG. 6 illustrates an example of a memory device 600 that supportsmemory with fine grain architectures in accordance with examples asdisclosed herein. Memory device 600 may be an example of memory device210 as described with reference to FIG. 2 . The memory device 600 mayinclude memory layers 630 (e.g., memory layers 230 as described withreference to FIG. 2 ). The memory device 600 may also include TSVs 635and bond pads 615 coupling the conductive path between the TSVs 635.Each memory layer 630 may also include an I/O circuit 605.

In some examples, each memory layer 630 may be configured to store datafor a host device (e.g., a host device 105 as described in FIG. 1 ).Data may be communicated to and from the memory layers 630 by an I/Ocircuit 605 and TSVs 635. That is, each memory layer 630 may have aregion of memory cells coupled with an I/O circuit 605. The I/O circuit605 may communicate data to and from the region of memory cells. EachI/O circuit 605 may include drivers, receivers, and other logic tocommunicate with the host device—e.g., the I/O circuit 605 may utilizedrivers to drive data to the host device and utilize receivers toreceive data from the host device. Because the memory device 600 iscoupled with the host device by a point-to-point connection, the I/Ocircuit 605 does not contain any buffers and communicates directly withthe host device. That is, the host device may transmit a signal directlyto the I/O circuit 605 to communicate with a memory cell.

In some examples, each I/O circuit 605 may also be coupled with a DQ pin610 for a given memory layer 630. For example, the I/O circuit 605-a maybe coupled with a DQ0 pin 610-a for the memory layer 630-a while I/Ocircuit 605-h may be coupled with a DQ0 pin 610-h for the memory layer630-h. The DQ pin 610 may be coupled with additional TSVs 635 that leadto conductive lines in a fine pitch organic substrate (e.g., substrate220 as described with reference to FIG. 2 ) that couples the memorydevice 600 with the host device. In some examples, the I/O circuits 605may reside in a first column position 620-a. That is, each I/O circuit605 of a given memory layer 630 may be in the same column position620-a.

In some examples, the I/O circuits 605 may drive and receive data orsignals through the TSVs 635. The I/O circuits may drive and receive thesignals and data in non-perpendicular (e.g., a waterfall) signal flowstructure. For example, the I/O circuit 605-a may drive signals to theDQ pin 610-a in a second column position 620-b. The I/O circuit 605-bfor the memory layer 630-b may drive a signal to a first TSV 635 in thesecond column position 620-b extending through the memory layer630-a—e.g., the first TSV 635 in the second column position 620-bextending through the memory layer 630-a may be coupled with an outputof memory layer 630-b by a bond pad 615. The signal may then be drivenfrom the first TSV 635 in the second column position 620-b to the DQ pin610-b in the third column position 620-c. A similar method of signaland/or data transfer may be implemented at each I/O circuit 605. Forexample, the I/O circuit 605-h located in the first column position620-a may eventually drive the signal to the DQ pin 610-h in the ninthcolumn position 620-i along the TSVs 635—e.g., starting by driving thesignal to a second TSV 635 in the second column position 620-b extendingthrough the memory layer 630-g, then to a third TSV 635 in the thirdcolumn position 620-c extending through the memory layer 630-f, so forthuntil the signal is driven to the DQ pin 610-h. Thus, although thesecond TSV 635 is located in the second column position 620-b above theDQ pin 610-a, the second TSV 625 may be dedicated to the memory layer630-h and the DQ pin 610-h. The I/O circuits 605 may receive signalsfrom the host device along the same TSV 635 path the signals are driven.

In some examples, the TSVS 635 not in the paths to the DQ pin 610 mayremain inactive. For example, TSV 635-b may remain inactive whilesignals and data are being driven. That is, the TSV 635-b is out of anydata or signal path to a given DQ pin 610 and may thus remain inactive.

By utilizing the waterfall structure for the signal and data pathsthrough the TSVs, the manufacturing of memory device 600 may besimplified. That is, each I/O circuit 605 and TSV may be manufactured inthe same column position 620 while still being configured to drivedifferent I/O circuits 605 to different DQ pins 610 at different columnpositions 620.

FIG. 7 illustrates an example of a timeline 700 that supports memorywith fine grain architectures in accordance with examples as disclosedherein. The timeline 700 shows events that may occur at a memory device(e.g., a memory device 210 as described with reference to FIG. 2 ). Thetimeline 700 indicates a timing for performing a training procedureand/or a frame synchronization procedure. During an active session 715,the memory device may be configured to identify the beginning of a framebased on a frame clock without reinitializing a frame trainingprocedure.

The timeline 700 may include a power-up event 705, an activation timeperiod 710, an active session 715, and a power-down event 720. When thememory device is powered down (e.g., after a power-down event 720), thememory device may be communicating little to no information with a hostdevice (e.g., host device 105 as described with reference to FIG. 1 ).As such, frame synchronization may not be utilized at that time. Apower-up event 705, is any event where the memory device begins anactive session 715. A power-up event 705 may be transition from anoff-state to an active state or from a low-power state to the activestate. The active session 715 may refer to a period of time when thememory device is servicing the memory needs of a host device—e.g.,performing access operations. The active session 715 may refer to acontinuous period of time where the memory device is operating withoutinterruption (e.g., without powering down in any way).

Before beginning the active session 715, the memory device may have toinitialize a number of parameters to provide full functionality to thehost device. The memory device may initialize these parameters duringthe activation time period 710. During the activation time period 710,the memory device may initiate a number of procedures to bringfunctionality to the memory device. For example, during the activationtime period 710, the memory device may initiate an eye synchronizationprocedure, a frame training procedure, a frame synchronizationprocedure, and/or other procedures, or a combination thereof.

During the activation time period 710, the memory device may receive aclock of the host device and may determine a rising or falling edge of asymbol. Once the memory device has identified a correct timing for thesymbols received from the host device, the memory device may initializea frame training procedure during the activation time period 710. Thatis, the memory device may synchronize a clock of the memory device withthe clock of the host device. In some examples, the clock of the hostmay be associated with a specific channel (e.g., channels 115 asdescribed with reference to FIG. 1 ). For example, the memory device mayinitiate a synchronization procedure for a clock of the host deviceassociated with the C/A channel. In such examples, synchronizing thememory clock associated with the CA channel with the host clockassociated with the CA channel may help facilitate a point-to-pointconnection between the memory device and the host device. That is,because the memory device does not include any buffer layers (and doesnot buffer any signals), the host device may transmit signals directlyto memory arrays (e.g., memory array 170 as described with reference toFIG. 1 ) and memory cells. The synchronization procedure may improve theefficiency of such point-to-point connections.

After the activation time period 710 and the synchronization procedure,the host device may communicate commands to the memory device during theactive session 715—e.g., commands to read data from or write data to thememory cells of the memory device. The memory device may perform theoperation associated with the command during the active session 715based on receiving the command. In some examples, after executing thecommand, the memory device may experience another power-down event 720and power down. That is, the memory device may cycle through thetimeline 700 over time as the host device services the memory device. Insome examples, the host device may initiate the power down—e.g., thepower-down event 720 may be a command from the host device. In otherexamples, the power-down may occur after a defined time period ofinactivity—e.g., after a duration during which the host device does nottransmit command to the memory device.

To reduce the quantity of conductive paths between the host device and amemory device a frame structure for communicating data and commands maybe used. In some memory systems, a conductive path may be dedicated to asignal that informs the memory device when a command is beingtransmitted. In such examples, the memory device may ignore data oncertain conductive paths when the enable signal is active. If the enableconductive path, the memory device may use a different mechanism tosynchronize when commands are being transmitted. In such examples, apacketized frame structure may be used. In such a structure, a frametiming (or packet timing) may be synchronized between the host deviceand memory device then information may be communicated in frames (e.g.,packets). In such examples, the information may not use headers or anenable signal thereby reducing signaling overhead and reducing aquantity of conductive paths.

FIG. 8 illustrates an example of a structure 800 for a frame trainingprocedure that supports memory with fine grain architectures inaccordance with examples as disclosed herein. The structure 800 showstwo instances (e.g., first instance 805 and second instances 810) of atraining pattern 815. Each instance 805, 810 shows a step in the frametraining procedure.

The frame training procedure is a process by which a memory device(e.g., a memory device 110 as described with reference to FIG. 1 )identifies a correct frame boundary. With the frame boundary, the memorydevice may generate a frame clock, which is used to identify frameboundaries (i.e., the start and stop of a frame) during an entire activesession. The frame clock may be based on a system clock, a symbollength, and a frame length. In some cases, the frame clock is a virtualclock that relies on the system clock for its timing. In other cases,the frame clock is a physical clock that is initialized to track theframes.

The training pattern 815 comprises a long train of symbols 820 that areset to predetermined symbol values used to identify a frame boundary.The training pattern 815 may comprise a plurality of training frames825, each training frame 825 comprising an ordered set of predeterminedsymbol values 830. An example of the symbol values may be a set of logic‘1’s followed by a set of logic ‘0’s, or vice versa. The training frame825 may have a frame length that is equal to a frame length of theframes transmitted by a host device (e.g., a host device 105 asdescribed with reference to FIG. 1 ) during the active session through afine pitch organic substrate (e.g., substrate 220 as described withreference to FIG. 1 ). That is, a portion of the channel communicatinginformation between the host device and the memory device may be routedthrough a conductive line (e.g., conductive lines 250 as described withreference to FIG. 2 ) in the fine pitch organic substrate. Using aplurality of training frames, the memory device may be configured todetermine a frame boundary 835 and generate a frame clock that is usedto identify the beginning of frames (or the end as the case may be)during the active session. That is, the memory device may be configuredto synchronize a clock of host device associated with CA channel (e.g.,channel 186 as described with reference to FIG. 1 ) with a clock of thememory device associated with the CA channel. In some examples, the CAchannel may be the conductive line routed through the fine pitch organicsubstrate (e.g., conductive lines 250 as described with reference toFIG. 2 ). Additionally, the fine pitch organic substrate may be coupledwith an organic substrate (e.g., substrate 215 as described withreference to FIG. 2 ).

During the activation time period and as part of a frame trainingprocedure, a host device may transmit a message to the memory device. Insome examples, the host device may include the training pattern 815 tothe memory device in the message. The memory device may determine whenthe training pattern is being transmitted so that it may be ready toinitialize the frame training procedure.

The host device may transmit the message to include an ordered set ofsymbols of a training frame of the training pattern that the memorydevice may identify. Additionally, the training pattern may include aset of training frames that each comprise an ordered set of symbolvalues. As shown in the first instance, 805, upon receiving the trainingpattern 815, the memory device may identify a symbol of the trainingpattern as a first frame boundary estimate 840. Using the first frameboundary estimate and/or a known frame length, the memory device maygenerate a first frame estimate 845. The first frame estimate 845 mayinclude a number of symbols of the training pattern 815 equal to theframe length of a training frame 825. The memory device may identify theordered set of symbols of the first frame estimate 845. The memorydevice may compare the ordered set of symbols of the first frameestimate 845 to the ordered set of predetermined symbol values 830.

If the ordered set of symbols of the first frame estimate 845 matchesthe ordered set of predetermined symbol values 830, the memory devicemay identify the rising edge of the symbol that comprises the firstframe boundary estimate 840 as the frame boundary. If the sets do notmatch, the memory device may perform a second frame boundary estimate850 and a second frame estimate 855 as shown in the second instance 810.The memory device may then repeat the same process of comparing the setof symbol values in the second frame estimate 855 to the ordered set ofpredetermined symbol values 830. This process may continue until acorrect frame boundary is found.

In some cases, the difference between the first frame boundary estimate840 and the second frame boundary estimate 850 may be one symbol. Insuch cases, the memory device may slip the boundary estimate one symbolupon determining that the frame boundary is not correct. In other cases,the memory device may select the second frame boundary estimate 850based on a predetermined symbol distance (e.g., one, two, three, four,five, six symbols, etc.). In some cases, the memory device may selectthe second frame boundary estimate based on the ordered set of symbolvalues found in the first frame estimate 845. For example, if the memorydevice knows that the predetermined set of symbol values is 111000 andthe set of symbol values of the first frame estimate 845 is 001110, thememory device may identify the third symbol of the first frame estimate845 as the second frame boundary estimate 850.

Once the memory device identifies the correct frame boundary, the memorydevice may generate a frame clock based on the frame synchronizationprocess. The frame clock may indicate the beginning of a new framethrough the active session. Using the frame clock, the memory device andthe host device may not use headers to indicate the location of frames,thereby freeing up more symbols for substantive data. In some cases, theframe boundary may be aligned with a rising edge of a first symbol (or afirst symbol period) in the frame. As such, the frame clock may also bealigned with a rising edge of the symbol period of the frame.

After the synchronization process, the memory device may receive acommand during a frame associated with the frame boundary identified bythe memory device. The memory device may receive the command from thehost device over the CA channel. In some examples, the frame may includea quantity of unit intervals—e.g., sixteen-unit intervals. The frameassociated with the CA channel may have a different unit of intervalsthan a unit of intervals for a second frame associated with a datachannel between the memory device and the host device. That is, thememory device may perform a separate synchronization process to find aframe boundary associated with the data channels. In some instances, theunit of intervals for frame associated with the data channel may betwice as large as the unit of intervals for the frame associated withthe command packet—e.g., a 2:1 command to data packet ratio. Forexample, the data frame may contain 32 bytes of information at four (4)nanosecond data frames while the command frame may include 16 bits attwo (2) nanosecond command frames.

In some instances, the frame boundaries associated with the CA channelmay be the same for independent, shared, or concurrent CA channels. Thatis, the memory device may be coupled with a plurality of CA channels andthe packetized protocol as described herein may be same across theplurality of CA channels, whether the channels are independent,concurrent, or shared.

In some examples, the following tables (e.g., Table 2 and Table 3) mayillustrate the various command the memory device may receive from thehost device during a given frame boundary. Table 2 may illustrate theinformation transmitted during the first eight (8) unit intervals whileTable 3 may illustrate the information transmitted during the secondeight (8) unit intervals of the frame boundary:

TABLE 2 Command UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7 NOP L L L V V V V V ACT0H L L BA3 BA2 BA1 BA0 V ACT1 H L H V V V V V REF H H L V V V V L REFPB HH L BA3 BA2 BA1 BA0 H MRS H H H M3 M2 M1 M0 OP7 PRE L L H BA3 BA2 BA1BA0 L PREA L L H BA3 BA2 BA1 BA0 H WR L H H BA3 BA2 BA1 BA0 L WRA L H HBA3 BA2 BA1 BA0 H RD L H L BA3 BA2 BA1 BA0 L RDA L H L BA3 BA2 BA1 BA0 H

TABLE 3 Command UI8 UI9 UI10 UI11 UI12 UI13 UI14 UI15 NOP V V V V V V VPAR ACT0 RA13 RA12 RA11 RA10 RA9 RA8 RA7 PAR ACT1 RA6 RA5 RA4 RA3 RA2RA1 RA0 PAR REF V V V V V V V PAR REFPB V V V V V V V PAR MRS OP6 OP5OP4 OP3 OP2 OP1 OP0 PAR PRE V V V V V V V PAR PREA V V V V V V V PAR WRV CA5 CA4 CA3 CA2 CA1 CA0 PAR WRA V CA5 CA4 CA3 CA2 CA1 CA0 PAR RD V CA5CA4 CA3 CA2 CA1 CA0 PAR RDA V CA5 CA4 CA3 CA2 CA1 CA0 PAR

In such examples, a first three-unit interval (UI0-UI2) may supply avoltage to the memory device according to a voltage associated with agiven command—e.g., a NOP (no operation command) may be associated witha low, low, low voltage. A next four-unit interval (UI3-UI6) may beassociated with a bank or memory address in the memory device. An eighthunit interval (UI7) may be associated with any additional voltagesassociated with the given command or an operation code—e.g., the NOPcommand may not be associated with additional voltages. A subsequentseven-unit interval (UI8-UI4) may be associated with row addresses orcolumn address. In the MRS command (mode register set command), theseunit intervals may be associated with additional operation codes orindications for the memory device. A final unit interval (UI15) may beassociated with a parity bit—e.g., error correction code to ensure thetransmission of the command was proper. A “V” may indicate there was nosignal or data communicated during that unit interval for the givencommand.

In some examples, the memory device may receive a NOP command—e.g., a nooperation command associated with a debugging or other rest operation.The memory device may also receive an ACT0 command—e.g., an activate 0command configured to activate a first portion of rows in the memorydevice. The memory device may also receive an ACT1 command—e.g., anactivate 1 command configured to activate a second portion of rows inthe memory device. In some cases, the memory device may receive a REFcommand—e.g., a refresh command configured to memory cells of memorycells in the memory device. In some instances, the memory device mayreceive a REFPB command—e.g., a refresh command configured to refreshbanks of memory cells in the memory device. In some examples, the memorydevice may receive an MRS command—e.g., a mode register set command toset a mode register in the memory device to a specific value. In somecases, the memory device may receive a PRE command—e.g., a prechargecommand for specific banks in the memory device. In some instances, thememory device may receive a PREA command—e.g., a precharge command forsome or all banks in the memory device. In some examples, the memorydevice may receive a WR command—e.g., a write command. In someinstances, the memory device may receive a WRA command—e.g., a writecommand including a precharge operation as well. In some examples, thememory device may receive a RD command—e.g., a read command. In someinstances, the memory device may receive an RDA command—e.g., a readcommand including a precharge operation as well.

FIG. 9 shows a block diagram 900 of a memory device 920 that supportsmemory with fine grain architectures in accordance with examples asdisclosed herein. The memory device 920 may be an example of aspects ofa memory device as described with reference to FIGS. 1 through 8 . Thememory device 920, or various components thereof, may be an example ofmeans for performing various aspects of memory with fine grainarchitectures as described herein. For example, the memory device 920may include a synchronization component 925, a receiver component 930,an operation component 935, an identifier component 940, a receivercomponent 945, or any combination thereof. Each of these components maycommunicate, directly or indirectly, with one another (e.g., via one ormore buses).

In some examples, the memory device 920 is coupled with a first organicsubstrate with a first pitch. In some examples, the first organicsubstrate is coupled with a second organic substrate with a second pitchlarger than the first pitch. In some examples, a portion of a CA channelis routed through a conductive line in the first organic substrate.

The synchronization component 925 may be configured as or otherwisesupport a means for performing a synchronization procedure tosynchronize a first clock of a host device associated with the CAchannel with a second clock of a memory device associated with the CAchannel. In some examples, to support performing the synchronizationprocedure, the synchronization component 925 may be configured as orotherwise support a means for synchronizing the second clock the memorydevice with the first frame boundary based at least in part ondetermining the first frame boundary.

The receiver component 930 may be configured as or otherwise support ameans for receiving, over the CA channel based at least in part onperforming the synchronization procedure, a command during a frameassociated with a frame boundary of the CA channel. The operationcomponent 935 may be configured as or otherwise support a means forperforming, by the memory device, an operation associated with thecommand based at least in part on receiving the command.

In some examples, the identifier component 940 may be configured as orotherwise support a means for identifying the frame boundary of theframe using the second clock based at least in part on performing thesynchronization procedure, where receiving the command is based at leastin part on identifying the frame boundary.

In some cases, to support performing the synchronization procedure, thereceiver component 945 may be configured as or otherwise support a meansfor receiving, from the host device, a signal including a trainingpattern of data. In some instances, to support performing thesynchronization procedure, the identifier component 940 may beconfigured as or otherwise support a means for determining a first frameboundary of a first frame of the signal based at least in part on thetraining pattern of data included in the signal, the frame includingmore than one symbol.

In some examples, the receiver component 945 may be configured as orotherwise support a means for receiving, from the host device, a messageindicating an ordered set of symbol values of a training frame of thetraining pattern of data, where determining the first frame boundary isbased at least in part on receiving the message. In some examples, thetraining pattern of data received by the receiver component 945 includesa set of training frames that each include an ordered set of symbolvalues. In some cases, the command received by the receiver component945 does not include a header. In some examples, the frame received bythe receiver component 945 includes a quantity of unit intervals. Insome instances, the quantity of unit intervals received by the receivercomponent 945 includes sixteen-unit intervals. In some examples, theframe associated with the CA channel includes a first quantity of unitintervals. In some cases, a second frame associated with a data channelbetween the memory device and the host device includes a second quantityof unit intervals. In some instances, the second quantity of unitintervals of the second frame associated with the data channel is twiceas large as the first quantity of unit intervals of the frame associatedwith the CA channel.

FIG. 10 shows a flowchart illustrating a method 1000 that supportsmemory with fine grain architectures in accordance with examples asdisclosed herein. The operations of method 1000 may be implemented by amemory device or its components as described herein. For example, theoperations of method 1000 may be performed by a memory device asdescribed with reference to FIGS. 1 through 9 . In some examples, amemory device may execute a set of instructions to control thefunctional elements of the device to perform the described functions.Additionally or alternatively, the memory device may perform aspects ofthe described functions using special-purpose hardware.

At 1005, the method may include performing a synchronization procedureto synchronize a first clock of a host device associated with a CAchannel with a second clock of a memory device associated with the CAchannel. The operations of 1005 may be performed in accordance withexamples as disclosed herein. In some examples, aspects of theoperations of 1005 may be performed by a synchronization component 925as described with reference to FIG. 9 .

At 1010, the method may include receiving, over the CA channel based atleast in part on performing the synchronization procedure, a commandduring a frame associated with a frame boundary of the CA channel. Theoperations of 1010 may be performed in accordance with examples asdisclosed herein. In some examples, aspects of the operations of 1010may be performed by a receiver component 930 as described with referenceto FIG. 9 .

At 1015, the method may include performing, by the memory device, anoperation associated with the command based at least in part onreceiving the command. The operations of 1015 may be performed inaccordance with examples as disclosed herein. In some examples, aspectsof the operations of 1015 may be performed by an operation component 935as described with reference to FIG. 9 .

In some examples, an apparatus as described herein may perform a methodor methods, such as the method 1000. The apparatus may include,features, circuitry, logic, means, or instructions (e.g., anon-transitory computer-readable medium storing instructions executableby a processor) for performing a synchronization procedure tosynchronize a first clock of a host device associated with a CA channelwith a second clock of a memory device associated with the CA channel,receiving, over the CA channel based at least in part on performing thesynchronization procedure, a command during a frame associated with aframe boundary of the CA channel, and performing, by the memory device,an operation associated with the command based at least in part onreceiving the command.

Some cases of the method 1000 and the apparatus described herein mayfurther include operations, features, circuitry, logic, means, orinstructions for identifying the frame boundary of the frame using thesecond clock based at least in part on performing the synchronizationprocedure, where receiving the command may be based at least in part onidentifying the frame boundary.

In some instances of the method 1000 and the apparatus described herein,the memory device may be coupled with a first organic substrate with afirst pitch, the first organic substrate may be coupled with a secondorganic substrate with a second pitch larger than the first pitch, and aportion of the CA channel may be routed through a conductive line in thefirst organic substrate.

In some examples of the method 1000 and the apparatus described herein,performing the synchronization procedure may include operations,features, circuitry, logic, means, or instructions for receiving, fromthe host device, a signal including a training pattern of data,determining a first frame boundary of a first frame of the signal basedat least in part on the training pattern of data included in the signal,the frame including more than one symbol, and synchronizing the secondclock the memory device with the first frame boundary based at least inpart on determining the first frame boundary.

Some cases of the method 1000 and the apparatus described herein mayfurther include operations, features, circuitry, logic, means, orinstructions for receiving, from the host device, a message indicatingan ordered set of symbol values of a training frame of the trainingpattern of data, where determining the first frame boundary may be basedat least in part on receiving the message.

In some instances of the method 1000 and the apparatus described herein,the training pattern of data includes a set of training frames that eachinclude an ordered set of symbol values.

In some examples of the method 1000 and the apparatus described herein,the command does not include a header.

In some cases of the method 1000 and the apparatus described herein, theframe includes a quantity of unit intervals.

In some instances of the method 1000 and the apparatus described herein,the quantity of unit intervals includes sixteen unit intervals.

In some examples of the method 1000 and the apparatus described herein,the frame associated with the CA channel includes a first quantity ofunit intervals and a second frame associated with a data channel betweenthe memory device and the host device includes a second quantity of unitintervals.

In some cases of the method 1000 and the apparatus described herein, thesecond quantity of unit intervals of the second frame associated withthe data channel may be twice as large as the first quantity of unitintervals of the frame associated with the CA channel.

It should be noted that the methods described herein describe possibleimplementations, and that the operations and the steps may be rearrangedor otherwise modified and that other implementations are possible.Further, portions from two or more of the methods may be combined.

An apparatus is described. The apparatus may include a memory device, afirst organic substrate including a plurality of first conductive linesarranged with a first pitch, the plurality of first conductive linesconfigured to power one or more components of the memory device, and asecond organic substrate coupled with the memory device and the firstorganic substrate, the second organic substrate including a plurality ofsecond conductive lines arranged with a second pitch smaller than thefirst pitch, where the plurality of second conductive lines routedthrough the second organic substrate are configured to couple the memorydevice with a host device.

In some examples of the apparatus, the first pitch of the first organicsubstrate includes may be greater than or equal to ten micrometers andthe second pitch of the second organic substrate may be less than orequal to two micrometers.

In some instances of the apparatus, the first organic substrate includesone or more of a first line parameter or a first space parameter thatmay be greater than or equal to ten micrometers and the second organicsubstrate includes one or more of a second line or a second spaceparameter that may be less than or equal to two micrometers.

In some cases of the apparatus, the memory device includes a pluralityof memory arrays that include a first memory array and a second memoryarray stacked on the first memory array, one or more column positionsmay be common to each memory array of the plurality of memory arrays,the first memory array includes a first I/O circuit coupled with a firstTSV, the first I/O circuit positioned at a first column position and thefirst TSV positioned at a second column position, the first memory arrayincluding a conductive path configured to route a second TSV of thefirst memory array at a third column position to a third TSV of thesecond memory array positioned at the second column position, and thesecond memory array including a second I/O circuit coupled with thethird TSV, the second I/O circuit positioned at the first columnposition and the second TSV positioned at the second column position.

In some examples of the apparatus, the first memory array includes afourth TSV at a fourth column position, the second memory array includesa fifth TSV at the fourth column position, the fifth TSV coupled withthe fourth TSV at the fourth column position, the fourth TSV and thefifth TSV may be configured to transfer power to the first memory arrayand the second memory array, the first TSV configured to communicatedata between the first memory array and the host device, and the secondTSV and the third TSV may be configured to communicate data between thesecond memory array and the host device.

In some instances of the apparatus, the memory device includes aplurality of memory arrays that include a first memory array and asecond memory array stacked on the first memory array, one or morecolumn positions may be common to each memory array of the plurality ofmemory arrays and each memory array of the plurality of memory arraysmay be configured to route signals from a first TSV at a first columnposition to a second TSV at a second column position.

In some cases of the apparatus, the memory device includes a firstmemory array including one or more memory cells, a first I/O areaextending in a first direction through the first memory array anddividing the first memory array into a first portion and a secondportion, and one or more second I/O areas extending a second directionthrough the first memory array, each of the one or more second I/O areasextending through the first portion and the second portion, and whereinthe first I/O area and the one or more second I/O areas occupy an areaof the first memory array that is devoid of memory cells.

In some examples of the apparatus, an I/O area of the one or more secondI/O areas includes a plurality of channels configured to communicateinformation between a region of memory cells of the first memory arrayand the host device, the region of memory cells including one or morebanks of memory cells positioned near the I/O area that includes theplurality of channels.

In some instances of the apparatus, the one or more second I/O areas maybe distributed throughout the first memory array to be near a pluralityof regions of the first memory array.

In some cases of the apparatus, an interface between the second organicsubstrate and the memory device, the interface including a pattern ofcontacts configured to route signals to different regions of the memorydevice, where at least some of the pattern of contacts may be positionedbeneath the one or more second I/O areas.

In some examples of the apparatus, the memory device includes aplurality of channels configured to communicate information between aregion of memory cells of a first memory array and the host device, theregion of memory cells including one or more banks of memory cellspositioned near an I/O area of the first memory array that includes theplurality of channels.

In some cases of the apparatus, the plurality of channels includes oneor more channels configured to communicate data between the region ofmemory cells and the host device, a command/address channel configuredto communicate commands and address information from the host device tothe first memory array, and one or more other channels.

In some instances of the apparatus, a channel of the plurality ofchannels includes a third conductive line coupling a memory cell in theregion of memory cells with a first interface in the first memory array,a fourth conductive line coupling the first interface in the firstmemory array with a second interface of the memory device, the fourthconductive line passing through one or more additional layers of thememory device, and the plurality of second conductive lines coupling thesecond interface of the memory device with the host device.

In some examples of the apparatus, the memory device includes aplurality of channels configured to communicate information between afirst region of memory cells of a first memory array and the host deviceand a second region of memory cells of the first memory array and thehost device, the first region of memory cells and the second region ofmemory cells including one or more banks of memory cells positioned nearan I/O area of the first memory array that includes the plurality ofchannels.

In some instances of the apparatus, the plurality of channels includes afirst set of channels dedicated to the first region of memory cells, asecond set of channels dedicated to the second region of memory cells,and a third set of channels shared by the first region of memory cellsand the second region of memory cells.

In some cases of the apparatus, the memory device includes a layerincluding one or more circuits to operate the memory device, a firstmemory array including one or more memory cells, and a second memoryarray including one or more memory cells.

In some instances of the apparatus, the one or more circuits of thelayer include self-test circuits to test one or more aspects of thefirst memory array or the second memory array.

In some cases of the apparatus, the one or more circuits in the layermay be not configured to buffer signals communicated over the pluralityof second conductive lines.

In some examples of the apparatus, a second conductive line of theplurality of second conductive lines includes a portion of apoint-to-point connection between the host device and a memory cell ofthe memory device.

In some cases of the apparatus, a second conductive line of theplurality of second conductive lines may have a first impedance that maybe less than a second impedance than a conductive line of a siliconinterposer.

Another apparatus is described. The apparatus may include a memorydevice, a first organic substrate including a first conductive line witha first pitch, the first organic substrate including a plane forpowering one or more components of the memory device, a second organicsubstrate coupled with the first organic substrate and including asecond conductive line with a second pitch smaller than the first pitch,the second conductive line routed through the second organic substratecouples the memory device with a host device, the memory device iscoupled with the second organic substrate, and a controller associatedwith the memory device and configured to cause the apparatus to performa synchronization procedure to synchronize a first clock of the hostdevice associated with a CA channel with a second clock of the memorydevice associated with the CA channel, receive, over the CA channelbased at least in part on performing the synchronization procedure, acommand during a frame associated with a frame boundary of the CAchannel, and perform, by the memory device, an operation associated withthe command based at least in part on receiving the command.

Information and signals described herein may be represented using any ofa variety of different technologies and techniques. For example, data,instructions, commands, information, signals, bits, symbols, and chipsthat may be referenced throughout the above description may berepresented by voltages, currents, electromagnetic waves, magneticfields or particles, optical fields or particles, or any combinationthereof. Some drawings may illustrate signals as a single signal,however, the signal may represent a bus of signals, where the bus mayhave a variety of bit widths.

The terms “electronic communication,” “conductive contact,” “connected,”and “coupled” may refer to a relationship between components thatsupports the flow of signals between the components. Components areconsidered in electronic communication with (or in conductive contactwith or connected with or coupled with) one another if there is anyconductive path between the components that can, at any time, supportthe flow of signals between the components. At any given time, theconductive path between components that are in electronic communicationwith each other (or in conductive contact with or connected with orcoupled with) may be an open circuit or a closed circuit based on theoperation of the device that includes the connected components. Theconductive path between connected components may be a direct conductivepath between the components or the conductive path between connectedcomponents may be an indirect conductive path that may includeintermediate components, such as switches, transistors, or othercomponents. In some examples, the flow of signals between the connectedcomponents may be interrupted for a time, for example, using one or moreintermediate components such as switches or transistors.

The term “coupling” refers to condition of moving from an open-circuitrelationship between components in which signals are not presentlycapable of being communicated between the components over a conductivepath to a closed-circuit relationship between components in whichsignals are capable of being communicated between components over theconductive path. When a component, such as a controller, couples othercomponents together, the component initiates a change that allowssignals to flow between the other components over a conductive path thatpreviously did not permit signals to flow.

The term “isolated” refers to a relationship between components in whichsignals are not presently capable of flowing between the components.Components are isolated from each other if there is an open circuitbetween them. For example, two components separated by a switch that ispositioned between the components are isolated from each other when theswitch is open. When a controller isolates two components, thecontroller affects a change that prevents signals from flowing betweenthe components using a conductive path that previously permitted signalsto flow.

The term “layer” or “level” used herein refers to a stratum or sheet ofa geometrical structure (e.g., relative to a substrate). Each layer orlevel may have three dimensions (e.g., height, width, and depth) and maycover at least a portion of a surface. For example, a layer or level maybe a three dimensional structure where two dimensions are greater than athird, e.g., a thin-film. Layers or levels may include differentelements, components, and/or materials. In some examples, one layer orlevel may be composed of two or more sublayers or sublevels.

As used herein, the term “substantially” means that the modifiedcharacteristic (e.g., a verb or adjective modified by the termsubstantially) need not be absolute but is close enough to achieve theadvantages of the characteristic.

The devices discussed herein, including a memory array, may be formed ona semiconductor substrate, such as silicon, germanium, silicon-germaniumalloy, gallium arsenide, gallium nitride, etc. In some examples, thesubstrate is a semiconductor wafer. In other examples, the substrate maybe a silicon-on-insulator (SOI) substrate, such as silicon-on-glass(SOG) or silicon-on-sapphire (SOP), or epitaxial layers of semiconductormaterials on another substrate. The conductivity of the substrate, orsub-regions of the substrate, may be controlled through doping usingvarious chemical species including, but not limited to, phosphorous,boron, or arsenic. Doping may be performed during the initial formationor growth of the substrate, by ion-implantation, or by any other dopingmeans.

A switching component or a transistor discussed herein may represent afield-effect transistor (FET) and comprise a three terminal deviceincluding a source, drain, and gate. The terminals may be connected toother electronic elements through conductive materials, e.g., metals.The source and drain may be conductive and may comprise a heavily-doped,e.g., degenerate, semiconductor region. The source and drain may beseparated by a lightly-doped semiconductor region or channel. If thechannel is n-type (i.e., majority carriers are electrons), then the FETmay be referred to as a n-type FET. If the channel is p-type (i.e.,majority carriers are holes), then the FET may be referred to as ap-type FET. The channel may be capped by an insulating gate oxide. Thechannel conductivity may be controlled by applying a voltage to thegate. For example, applying a positive voltage or negative voltage to ann-type FET or a p-type FET, respectively, may result in the channelbecoming conductive. A transistor may be “on” or “activated” when avoltage greater than or equal to the transistor's threshold voltage isapplied to the transistor gate. The transistor may be “off” or“deactivated” when a voltage less than the transistor's thresholdvoltage is applied to the transistor gate.

The description set forth herein, in connection with the appendeddrawings, describes example configurations and does not represent allthe examples that may be implemented or that are within the scope of theclaims. The term “exemplary” used herein means “serving as an example,instance, or illustration,” and not “preferred” or “advantageous overother examples.” The detailed description includes specific details toproviding an understanding of the described techniques. Thesetechniques, however, may be practiced without these specific details. Insome instances, well-known structures and devices are shown in blockdiagram form to avoid obscuring the concepts of the described examples.

In the appended figures, similar components or features may have thesame reference label. Further, various components of the same type maybe distinguished by following the reference label by a dash and a secondlabel that distinguishes among the similar components. If just the firstreference label is used in the specification, the description isapplicable to any one of the similar components having the same firstreference label irrespective of the second reference label.

The functions described herein may be implemented in hardware, softwareexecuted by a processor, firmware, or any combination thereof. Ifimplemented in software executed by a processor, the functions may bestored on or transmitted over as one or more instructions or code on acomputer-readable medium. Other examples and implementations are withinthe scope of the disclosure and appended claims. For example, due to thenature of software, functions described herein can be implemented usingsoftware executed by a processor, hardware, firmware, hardwiring, orcombinations of any of these. Features implementing functions may alsobe physically located at various positions, including being distributedsuch that portions of functions are implemented at different physicallocations.

For example, the various illustrative blocks and modules described inconnection with the disclosure herein may be implemented or performedwith a general-purpose processor, a DSP, an ASIC, an FPGA or otherprogrammable logic device, discrete gate or transistor logic, discretehardware components, or any combination thereof designed to perform thefunctions described herein. A general-purpose processor may be amicroprocessor, but in the alternative, the processor may be anyprocessor, controller, microcontroller, or state machine. A processormay also be implemented as a combination of computing devices (e.g., acombination of a DSP and a microprocessor, multiple microprocessors, oneor more microprocessors in conjunction with a DSP core, or any othersuch configuration).

As used herein, including in the claims, “or” as used in a list of items(for example, a list of items prefaced by a phrase such as “at least oneof” or “one or more of”) indicates an inclusive list such that, forexample, a list of at least one of A, B, or C means A or B or C or AB orAC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase“based on” shall not be construed as a reference to a closed set ofconditions. For example, an exemplary step that is described as “basedon condition A” may be based on both a condition A and a condition Bwithout departing from the scope of the present disclosure. In otherwords, as used herein, the phrase “based on” shall be construed in thesame manner as the phrase “based at least in part on.”

Computer-readable media includes both non-transitory computer storagemedia and communication media including any medium that facilitatestransfer of a computer program from one place to another. Anon-transitory storage medium may be any available medium that can beaccessed by a general purpose or special purpose computer. By way ofexample, and not limitation, non-transitory computer-readable media cancomprise RAM, ROM, electrically erasable programmable read-only memory(EEPROM), compact disk (CD) ROM or other optical disk storage, magneticdisk storage or other magnetic storage devices, or any othernon-transitory medium that can be used to carry or store desired programcode means in the form of instructions or data structures and that canbe accessed by a general-purpose or special-purpose computer, or ageneral-purpose or special-purpose processor. Also, any connection isproperly termed a computer-readable medium. For example, if the softwareis transmitted from a website, server, or other remote source using acoaxial cable, fiber optic cable, twisted pair, digital subscriber line(DSL), or wireless technologies such as infrared, radio, and microwave,then the coaxial cable, fiber optic cable, twisted pair, digitalsubscriber line (DSL), or wireless technologies such as infrared, radio,and microwave are included in the definition of medium. Disk and disc,as used herein, include CD, laser disc, optical disc, digital versatiledisc (DVD), floppy disk and Blu-ray disc where disks usually reproducedata magnetically, while discs reproduce data optically with lasers.Combinations of the above are also included within the scope ofcomputer-readable media.

The description herein is provided to enable a person skilled in the artto make or use the disclosure. Various modifications to the disclosurewill be apparent to those skilled in the art, and the generic principlesdefined herein may be applied to other variations without departing fromthe scope of the disclosure. Thus, the disclosure is not limited to theexamples and designs described herein, but is to be accorded thebroadest scope consistent with the principles and novel featuresdisclosed herein.

What is claimed is:
 1. An apparatus, comprising: a memory device,wherein the memory device comprises a plurality of memory arrays thatinclude a first memory array and a second memory array stacked on thefirst memory array, one or more column positions are common to eachmemory array of the plurality of memory arrays; a first organicsubstrate comprising a plurality of first conductive lines arranged witha first pitch, the plurality of first conductive lines configured topower one or more components of the memory device; and a second organicsubstrate coupled with the memory device and the first organicsubstrate, the second organic substrate comprising a plurality of secondconductive lines arranged with a second pitch smaller than the firstpitch, wherein the plurality of second conductive lines routed throughthe second organic substrate are configured to couple the memory devicewith a host device.
 2. The apparatus of claim 1, wherein: the firstpitch of the first organic substrate is greater than or equal to tenmicrometers; and the second pitch of the second organic substrate isless than or equal to two micrometers.
 3. The apparatus of claim 1,wherein: the first organic substrate includes one or more of a firstline parameter or a first space parameter that is greater than or equalto ten micrometers; and the second organic substrate includes one ormore of a second line or a second space parameter that is less than orequal to two micrometers.
 4. The apparatus of claim 1, wherein: thefirst memory array includes a first input/output (I/O) circuit coupledwith a first through-silicon via (TSV), the first I/O circuit positionedat a first column position and the first TSV positioned at a secondcolumn position; the first memory array including a conductive pathconfigured to route a second TSV of the first memory array at a thirdcolumn position to a third TSV of the second memory array positioned atthe second column position; and the second memory array including asecond I/O circuit coupled with the third TSV, the second I/O circuitpositioned at the first column position and the second TSV positioned atthe second column position.
 5. The apparatus of claim 4, wherein: thefirst memory array includes a fourth TSV at a fourth column position;the second memory array includes a fifth TSV at the fourth columnposition, the fifth TSV coupled with the fourth TSV at the fourth columnposition; the fourth TSV and the fifth TSV are configured to transferpower to the first memory array and the second memory array; the firstTSV configured to communicate data between the first memory array andthe host device; and the second TSV and the third TSV are configured tocommunicate data between the second memory array and the host device. 6.The apparatus of claim 1, wherein: each memory array of the plurality ofmemory arrays is configured to route signals from a firstthrough-silicon via (TSV) at a first column position to a second TSV ata second column position.
 7. The apparatus of claim 1, wherein thememory device comprises: the first memory array comprising: one or morememory cells; a first input/output (I/O) area extending in a firstdirection through the first memory array and dividing the first memoryarray into a first portion and a second portion; and one or more secondI/O areas extending a second direction through the first memory array,each of the one or more second I/O areas extending through the firstportion and the second portion; wherein the first I/O area and the oneor more second I/O areas occupy an area of the first memory array thatis devoid of memory cells.
 8. The apparatus of claim 7, wherein an I/Oarea of the one or more second I/O areas comprises a plurality ofchannels configured to communicate information between a region ofmemory cells of the first memory array and the host device, the regionof memory cells comprising one or more banks of memory cells positionednear the I/O area that includes the plurality of channels.
 9. Theapparatus of claim 7, wherein the one or more second I/O areas aredistributed throughout the first memory array to be near a plurality ofregions of the first memory array.
 10. The apparatus of claim 7, furthercomprising: an interface between the second organic substrate and thememory device, the interface comprising a pattern of contacts configuredto route signals to different regions of the memory device, wherein atleast some of the pattern of contacts are positioned beneath the one ormore second I/O areas.
 11. The apparatus of claim 1, wherein the memorydevice comprises: a plurality of channels configured to communicateinformation between a region of memory cells of the first memory arrayand the host device, the region of memory cells comprising one or morebanks of memory cells positioned near an I/O area of the first memoryarray that includes the plurality of channels.
 12. The apparatus ofclaim 11, wherein the plurality of channels comprises: one or morechannels configured to communicate data between the region of memorycells and the host device, a command/address channel configured tocommunicate commands and address information from the host device to thefirst memory array, and one or more other channels.
 13. The apparatus ofclaim 11, wherein a channel of the plurality of channels comprises: athird conductive line coupling a memory cell in the region of memorycells with a first interface in the first memory array; a fourthconductive line coupling the first interface in the first memory arraywith a second interface of the memory device, the fourth conductive linepassing through one or more additional layers of the memory device; andthe plurality of second conductive lines coupling the second interfaceof the memory device with the host device.
 14. The apparatus of claim 1,wherein the memory device comprises: a plurality of channels configuredto communicate information between a first region of memory cells of thefirst memory array and the host device and a second region of memorycells of the first memory array and the host device, the first region ofmemory cells and the second region of memory cells comprising one ormore banks of memory cells positioned near an I/O area of the firstmemory array that includes the plurality of channels.
 15. The apparatusof claim 14, wherein the plurality of channels comprises: a first set ofchannels dedicated to the first region of memory cells; a second set ofchannels dedicated to the second region of memory cells; and a third setof channels shared by the first region of memory cells and the secondregion of memory cells.
 16. The apparatus of claim 1, wherein the memorydevice comprises: a layer comprising one or more circuits to operate thememory device; the first memory array comprising one or more memorycells; and the second memory array comprising one or more memory cells.17. The apparatus of claim 16, wherein the one or more circuits of thelayer comprise self-test circuits to test one or more aspects of thefirst memory array or the second memory array.
 18. The apparatus ofclaim 16, wherein the one or more circuits in the layer are notconfigured to buffer signals communicated over the plurality of secondconductive lines.
 19. The apparatus of claim 1, wherein a secondconductive line of the plurality of second conductive lines comprises aportion of a point-to-point connection between the host device and amemory cell of the memory device.
 20. The apparatus of claim 1, whereina second conductive line of the plurality of second conductive lines hasa first impedance that is less than a second impedance than a conductiveline of a silicon interposer.
 21. A method, comprising: performing asynchronization procedure to synchronize a first clock of a host deviceassociated with a command/address (CA) channel with a second clock of amemory device associated with the CA channel; receiving, over the CAchannel based at least in part on performing the synchronizationprocedure, a command during a frame associated with a frame boundary ofthe CA channel; and performing, by the memory device, an operationassociated with the command based at least in part on receiving thecommand.
 22. The method of claim 21, further comprising: identifying theframe boundary of the frame using the second clock based at least inpart on performing the synchronization procedure, wherein receiving thecommand is based at least in part on identifying the frame boundary. 23.The method of claim 21, wherein: the memory device is coupled with afirst organic substrate with a first pitch; the first organic substrateis coupled with a second organic substrate with a second pitch largerthan the first pitch; and a portion of the CA channel is routed througha conductive line in the first organic substrate.
 24. The method ofclaim 21, wherein performing the synchronization procedure comprises:receiving, from the host device, a signal comprising a training patternof data; determining a first frame boundary of a first frame of thesignal based at least in part on the training pattern of data includedin the signal, the frame comprising more than one symbol; andsynchronizing the second clock the memory device with the first frameboundary based at least in part on determining the first frame boundary.25. The method of claim 24, further comprising: receiving, from the hostdevice, a message indicating an ordered set of symbol values of atraining frame of the training pattern of data, wherein determining thefirst frame boundary is based at least in part on receiving the message.26. The method of claim 24, wherein the training pattern of datacomprises a set of training frames that each comprise an ordered set ofsymbol values.
 27. The method of claim 21, wherein the command does notinclude a header.
 28. The method of claim 21, wherein the framecomprises a quantity of unit intervals.
 29. The method of claim 28,wherein the quantity of unit intervals comprises sixteen unit intervals.30. The method of claim 21, wherein: the frame associated with the CAchannel comprises a first quantity of unit intervals; and a second frameassociated with a data channel between the memory device and the hostdevice comprises a second quantity of unit intervals.
 31. The method ofclaim 30, wherein the second quantity of unit intervals of the secondframe associated with the data channel is twice as large as the firstquantity of unit intervals of the frame associated with the CA channel.32. An apparatus, comprising: a memory device; a first organic substratecomprising a first conductive line with a first pitch, the first organicsubstrate comprising a plane for powering one or more components of thememory device; a second organic substrate coupled with the first organicsubstrate and comprising a second conductive line with a second pitchsmaller than the first pitch, the second conductive line routed throughthe second organic substrate couples the memory device with a hostdevice, the memory device is coupled with the second organic substrate;and a controller associated with the memory device and configured tocause the apparatus to: perform a synchronization procedure tosynchronize a first clock of the host device associated with acommand/address (CA) channel with a second clock of the memory deviceassociated with the CA channel; receive, over the CA channel based atleast in part on performing the synchronization procedure, a commandduring a frame associated with a frame boundary of the CA channel; andperform, by the memory device, an operation associated with the commandbased at least in part on receiving the command.